Automated Parasitic Extraction for IC Packages

Turbo Package Analyzer™ (TPA) provides the package extraction and automation capability needed to address the electrical requirements of today's complex high-performance SiP, chip-scale, flip-chip, ball-grid array, and wire-bond. With TPA, IC and package designers of analog/RF and high-speed digital applications are able to fully characterize an entire package structure and automatically extract lumped or distributed RLC values for use with Nexxim® or alternative SPICE-compatible tools to perform subsequent transient analyses, such as crosstalk, overshoot, and TDR. TPA further enables the prediction of IC package performance and compatibility, facilitating performance trade-off analysis before a design is committed to fabrication. TPA couples with leading electronic package layout tools to accurately model package interconnect elements, such as non-orthogonal traces, vias, wire-bonds, and solder balls, and to take into account the non-ideal ground planes prevalent in these advanced IC package designs.

New in TPA v5.0

• DC resistance computation for 3D structures
  • Automated net-by-net full-package DC resistance extraction using a volumetric (tetrahedral) mesh
• Ability to designate source and sink terminal assignment on any given net
• New 2D layout editor and 3D viewer
  • Create advanced wire-bond or flip-chip designs from scratch or modify/correct designs imported from third-party layout tools
  • System-in-Package (SiP) design with multiple wire-bond configurations including Trace-to-trace, Die-to-die, and Cascaded
  • User-defined wire-bond profiles expanding shapes from JEDEC 4- and 5-point to include arbitrary polylines
  • Complex solderball models capture true shape and subsequent electrical performance of solderballs and flip-chip solder-bumps
  • New layer stack-up editor
  • New via pad stack editor
• VB scripting support
• Validation check to verify setup, including detection of self-intersecting polygons; disjoint nets; overlapping (DC-shorted) nets, vias and bond wires; illegal connections between bonding pads and bond wires
• Available for Microsoft Windows® XP Professional x64

TPA fully characterizes an entire package structure and automatically produces lumped or distributed RLC (Resistance, Inductance, and Capacitance) values for any lead or coupled groups of leads in matrix format or in SPICE sub-circuit format. These models can be generated directly from package layout tools coming from Synopsys, Cadence and Zuken, and exported into existing SPICE tools (SPICE/IBIS format) for subsequent timing analyses.

Working in Your Design Flow
TPA can be integrated directly into electronic package layout tools, such as Synopsys Encore™, Cadence Advanced Package Designer (APD), and Zuken CR-5000, to provide package engineers with a seamless design flow, automatically generating RLC models. The resulting electrical models can then be exported to and analyzed within Ansoft Designer®/DesignerSI™, Nexxim® or other SPICE-compatible circuit tools. 

 

Product Features

• Quasi-static electromagnetic field analysis using 3D Boundary Element Method (BEM) and Fast Multipole Method (FMM)
  • Takes into consideration skin effect and conductor loss
  • Extraction of R, L, and C parasitic components
• Automatic partitioning and extraction of parasitics for entire package or partial section thereof:
  • Partition by number of nets and coupling distance
  • Automatic grouping of nets and analysis
  • Sequential analysis of net groups and full matrix reconstruction
    • Spice-compatible/IBIS model including all pins 
• Equivalent circuit model creation (SPICE sub-circuits / lumped models)
  • Export for HSpice®, PSpice®, Spectre® RF, and other Berkeley-compatible SPICE tools
  • Cadence DML, Synopsys SPEF, and IBIS .pkg model
• CAD import and editing:
  • Import full or partial layouts including layers, pad stacks, nets, bond wires, etc.
  • User interface supports editing of layers, bond wires, solderballs and bumps
• Layout integration through AnsoftLinks™
  • Cadence APD
  • Cadence SiP Digital/RF
  • Mentor Graphics PADS Layout™
  • Sigrity UPD

What's Your Focus

IC packaging

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With the introduction of deep-submicron and system-on-chip integrated circuits, complex packages are now key components of high-performance electronic designs. Consequently, the inclusion of the electrical behavior of complex IC packages is a necessity to successfully simulate and deliver silicon. To shorten the design cycle, engineers require package-level design and analysis tools that are capable of handling the multilayer, custom-designed packages of flip chip, ball grid arrays (BGA), chip scale packages (CSP) and system-in-package (SiP). TPA addresses those design and analysis needs.