IntroductionThe Xtensa LX is a licensable, configurable 32-bit RISC processor core from Tensilica. Announced in May 2004,Xtensa LX is the sixth-generation Xtensa architecture, succeeding the Xtensa V, which was announced in August 2002. The Xtensa LX core targets a wide variety of applications,from low-power consumer electronics to high-performance communications infrastructure equipment. Since its founding in 1997, Tensilica has emphasized instruction-set configurability as the primary feature that distinguishes Xtensa from other core offerings. At its heart,
Xtensa LX is essentially a typical 32-bit RISC core with mixed-width 16- and 24-bit instructions. However, the Xtensa LX instruction set is configurable by licensees using a Verilog-like language called TIE (Tensilica Instruction Extension).Custom instructions added through the TIE language are compiled by Tensilica-provided tools and the associated new hardware is automatically inserted into a synthesizable model of the core. TIE supports the addition of new instructions that support operations ranging in complexity from simple arithmetic to complex, multi-stage computations that can add many thousands of gates to the Xtensa core. The Tensilica processor generator tool also generates a C/C++ compiler and cycle-accurate instruction-level simulator that are aware of the added instructions. Once a licensee is satisfied with the simulated results, the customized core can be implemented using logic synthesis tools and integrated into an ASIC design. Tensilica has recently announced a new TIE-generating compiler called XPRES. In conjunction with the Tensilica Xtensa C Compiler, XPRES is capable of identifying the performance-critical regions of C/C++ application source code and automatically generating custom instructions that improve performance on this code. The tool generates many different combinations of candidate custom instructions,allowing the licensee to select the best instructions or manually fine-tune them. A new feature of the Xtensa LX architecture is a VLIW instruction format called FLIX (Flexible-Length Instruction Xtensions). FLIX adds 32- and 64-bit instruction word formats to the base 16- and 24-bit formats found in previous generation Xtensa cores. The FLIX instruction formats support variable-length multi-issue instruction capability for custom instructions written in TIE. Xtensa LX can freely interleave a stream of 16-, 24-, and either 32- or 64-bit instructions without mode changes or stalls. FLIX and TIE are the enabling technologies of Vectra LX, Tensilica’s off-theshelf DSP-oriented instruction set add-on for the Xtensa LX core. Vectra LX is a packaged group of powerful instructions designed to accelerate DSP applications. Vectra LX adds a quad-MAC unit and a significant number of single-instruction, multiple-data (SIMD) instructions to the base Xtensa instruction set. Vectra LX also adds a bank of sixteen 160-bit vector registers and a second 128-bit load/store unit (for a total of 256-bits/cycle of data memory bandwidth) to the base core. For more information on Tensilica Xtensa LX Processor with Vectra LX Click Here | 
